PCI Express Technology

PCI(Peripheral Component Interconnect)是一种由英特尔(Intel)公司1991年推出的用于定义局部总线的标准。此标准允许在计算机内安装多达10个遵从PCI标准的扩展卡。

PCI Express Technology

• Link Initialization & Training
  • Link Training and Status State Machine (LTSSM)
    • The LTSSM consists of 11 top‐level states: Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Hot Reset, Loopback, and Disable
    • can be grouped into five categories
      • Link Training states
        • When exiting from any type of Reset,the flow of this states:Detect => Polling => Configuration => L0
      • Re‐Training (Recovery) state
        • entered for a variety of reasons:changing back from a low‐power Link state or changingthe Link bandwidth
      • Software driven Power Management states
      • Active‐State Power Management (ASPM) states
      • Other states
    • Overview of LTSSM States
      • Detect
        • device electrically detects a Receiver is present at the far end of the Link
      • Polling
        • Transmitters begin to send TS1s and TS2s,Receivers can use them to accomplish the following
          • Achieve Bit Lock
          • Acquire Symbol Lock or Block Lock
          • Correct Lane polarity inversion
          • Learn available Lane data rates
          • Initiate the Compliance test sequence
      • Configuration
        • Upstream and Downstream components exchange TS1s and TS2s at 2.5 GT/s to accomplish the following
          • Determine Link width
          • Assign Lane numbers
          • Optionally check for Lane reversal and correct it
          • Deskew Lane‐to‐Lane timing differences
      • L0
        • normal states
      • Recovery
        • In Recovery,Bit Lock and Symbol/Block Lock are re‐established in a manner similar to that used in the Polling state but it typically takes much less time
      • L0s
        • It’s entered when one Transmitter sends the EIOS while in the L0 state.Exit from L0s involves sending FTSs to quickly re‐acquire Bit and Symbol/Block Lock
      • L1
        • Entry into L1 involves a negotiation between both Link partners,and can occur in one of two ways
          • autonomous with ASPM
          • power management software issuing a commanding a device to a low‐power state
      • L2
        • main power to the devices is turned off,small amount of power is still available from the Vaux source
      • Loopback
        • When adevice sees two consecutive TS1s with the Loopback bit set, it enters the Loopback state
      • Disable
      • Hot Reset
        • When a Receiver sees two consecutive TS1s with the Hot Reset bit set, it must reset its device
    • Detect State
      • Introduction
      • Detect.Quiet
        • must be entered within 20 ms after Reset
        • properties of this substate
          • The Transmitter starts in Electrical Idle
          • The intended data rate is set to 2.5 GT/s
          • The Physical Layer’s status bit (LinkUp = 0) informs the Data Link Layer that the Link is not operational.
        • Exit to “Detect.Active”
          • after a 12 ms timeout or when any Lane exits Electrical Idle.
      • Detect.Active
        • Transmitter tests whether a Receiver is connected on each Lane by setting a DC common mode voltage of any value in the legal range and then changing it.If a Receiver is attached, the charge time will be much longer, making it easy to recognize.
        • Exit to “Detect.Quiet”
          • If no Lanes detect a Receiver.The loop between them is repeated every 12ms, as long as no Receiver is detected
        • Exit to “Polling State”
          • If a receiver is detected on all Lanes.The Lanes must now drive a DC common voltage within the 0 ‐ 3.6 V VTX‐CM‐DC spec.
        • Special Case
          • If some but not all Lanes of a device are connected to a Receiver, then wait 12 ms and try it again. If the same Lanes detect a Receiver the second time, exit to the Polling state, otherwise go back to Detect.Quiet.
    • Polling State
      • Introduction
        • TS1s and TS2s are exchanged between the two connected devices
      • Polling.Active
        • During Polling.Active
          • Transmitters send a minimum of 1024 consecutive TS1s on all detected Lanes
          • Some notes
            • The PAD Symbol must be used in the Lane and Link Number fields of the TS1s.
            • All data rates a device supports must be advertised
            • Receivers use the incoming TS1s to acquire Bit Lock and then either Symbol Lock for the lower rates, or Block Alignment for 8.0 GT/s
        • Exit to “Polling.Configuration”
          • after sending at least 1024 TS1s ALL detected Lanes receive 8 consecutive training sequences that satisfy one of the following conditions:
            • TS1s with Link and Lane set to PAD were received with the Compli‐ ance Receive bit cleared to 0b
            • TS1s with Link and Lane set to PAD were received with the Loopback bit of Symbol 5 set to 1b
            • TS2s were received with Link and Lane set to PAD
          • If the conditions above are not met, then after a 24ms timeout, if at least 1024 TS1s were sent after receiving a TS1, and ANY detected Lane received eight consecutive TS1 or TS2 Ordered Sets with the Lane and Link numbers set to PAD, and one of the following is true:
            • TS1s with Link and Lane set to PAD were received with the Compli‐ ance Receive (bit 4 of Symbol 5) cleared to 0b
            • TS1s with Link and Lane set to PAD were received with the Loopback (bit 2 of Symbol 5) set to 1b.
            • TS2s were received with Link and Lane set to PAD