导图社区 AHB协议学习
AHB总线规范是AMBA总线规范的一部分,AMBA总线规范是ARM公司提出的总线规范,被大多数SoC设计采用,它规定了AHB (Advanced High-performance Bus)、ASB (Advanced System Bus)、APB (Advanced Peripheral Bus)。
编辑于2021-07-13 17:14:48AHB总线规范是AMBA总线规范的一部分,AMBA总线规范是ARM公司提出的总线规范,被大多数SoC设计采用,它规定了AHB (Advanced High-performance Bus)、ASB (Advanced System Bus)、APB (Advanced Peripheral Bus)。
APB主要用来连接高性能低带宽的外围设备,在APB总线系统中,只有一个master,其他的都是slave。一般情况下,APB挂在AHB总线系统下,通过AHB-APB Bridge将事务在AHB总线系统之间进行转化,此时Bridgre即为APB的master,其他的外围设备均为slave。
PCI(Peripheral Component Interconnect)是一种由英特尔(Intel)公司1991年推出的用于定义局部总线的标准。此标准允许在计算机内安装多达10个遵从PCI标准的扩展卡。
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AHB总线规范是AMBA总线规范的一部分,AMBA总线规范是ARM公司提出的总线规范,被大多数SoC设计采用,它规定了AHB (Advanced High-performance Bus)、ASB (Advanced System Bus)、APB (Advanced Peripheral Bus)。
APB主要用来连接高性能低带宽的外围设备,在APB总线系统中,只有一个master,其他的都是slave。一般情况下,APB挂在AHB总线系统下,通过AHB-APB Bridge将事务在AHB总线系统之间进行转化,此时Bridgre即为APB的master,其他的外围设备均为slave。
PCI(Peripheral Component Interconnect)是一种由英特尔(Intel)公司1991年推出的用于定义局部总线的标准。此标准允许在计算机内安装多达10个遵从PCI标准的扩展卡。
AHB协议学习
Introductoin
Features
Burst transfers
Single clock-edge operation
Non-tristate implementation
Wide data bus configurations, 64, 128, 256, 512, and 1024 bits
AHB block diagram
Master interface
Slave interface
Operation
Single
Incrementing bursts that do not wrap at address boundaries
Wrapping bursts that wrap at particular address boundaries
Signal Descriptions
Global signals
Master signals
Slave signals
Decoder signals
Transfers
Basic transfers
A transfer consists of two phases
Address:Lasts for a single HCLK cycle unless its extended by the previous bus transfer
Data:Might require several HCLK cycles. Use the HREADY signal to control the number of clock cycles required to complete the transfer
simplest transfer is one with no wait states
Read transfer
Write transfer
The address phase of any transfer occurs during the data phase of the previous transfer
transfer with wait states
Read transfer
Write transfer
Multiple transfers
Transfer types
Transfer type examples
Locked transfers
This signal indicates to any slave that the current transfer sequence is indivisible and must therefore be processed before any other transfers are processed
After a locked transfer, it is recommended that the master inserts an IDLE transfer.
Transfer size
The transfer size set by HSIZE must be less than or equal to the width of the data bus
However, they must remain constant throughout a burst transfer.
Burst operation
Masters must not attempt to start an incrementing burst that crosses a 1KB address boundary
The burst size indicates the number of beats in the burst and not the number of bytes transferred
All transfers in a burst must be aligned to the address boundary equal to the size of the transfer. For example, word transfers must align to word address boundaries (HADDR[1:0] = 0b00), and halfword transfers to halfword address boundaries (HADDR[0] = 0).
Burst termination after a BUSY transfer
After a burst has started, the master uses BUSY transfers if it requires more time before continuing with the next transfer in the burst.
The protocol does not permit a master to end a burst with a BUSY transfer for fixed length bursts of type:Incrementing INCR4, INCR8, and INCR16;Wrapping WRAP4, WRAP8, and WRAP16
The master is not permitted to perform a BUSY transfer immediately after a SINGLE burst. SINGLE bursts must be followed by an IDLE transfer or a NONSEQ transfer
Early burst termination
Slave error response
If the master does not complete that burst then there is no requirement for it to rebuild the burst when it next accesses that slave
Multi-layer interconnect termination
Burst examples
Four-beat wrapping burst, WRAP4
Four-beat incrementing burst, INCR4
Eight-beat wrapping burst, WRAP8
Because the burst is an eight-beat burst of word transfers, the address wraps at 32-byte boundaries, and the transfer to address 0x3C is followed by a transfer to address 0x20.
Eight-beat incrementing burst, INCR8
Undefined length bursts, INCR
Waited transfers
Slaves use HREADYOUT to insert wait states if they require more time to provide or sample the data
Transfer type changes during wait states
When the slave is requesting wait states, the master must not change the transfer type, except as described in:
IDLE transfer
During a waited transfer, the master is permitted to change the transfer type from IDLE to NONSEQ. When the HTRANS transfer type changes to NONSEQ the master must keep HTRANS constant, until HREADY is HIGH
BUSY transfer, fixed length burst
During a waited transfer for a fixed length burst, the master is permitted to change the transfer type from BUSY to SEQ. When the HTRANS transfer type changes to SEQ the master must keep HTRANS constant, until HREADY is HIGH.
Because BUSY transfers must only be inserted between successive beats of a burst, this does not apply to SINGLE bursts. Therefore this situation applies to the following burst types: • INCR4, INCR8, and INCR16. • WRAP4, WRAP8, and WRAP16
BUSY transfer, undefined length burst
During a waited transfer for an undefined length burst, INCR, the master is permitted to change from BUSY to any other transfer type, when HREADY is LOW. The burst continues if a SEQ transfer is performed but terminates if an IDLE or NONSEQ transfer is performed.
Address changes during wait states
When the slave is requesting wait states, the master can only change the address once, except as described in:
During an IDLE transfer
During a waited transfer, the master is permitted to change the address for IDLE transfers. When the HTRANS transfer type changes to NONSEQ the master must keep the address constant, until HREADY is HIGH.
After an ERROR response
During a waited transfer, if the slave responds with an ERROR response then the master is permitted to change the address when HREADY is LOW.
Protection control
The HPROT control signals have exactly the same timing as the address bus. However, they must remain constant throughout a burst transfer
Memory types
Bus Interconnection
Address decoding
The minimum address space that can be allocated to a single slave is 1KB
All masters are designed so that they do not perform incrementing transfers over a 1KB address boundary
If a system design does not contain a completely filled memory map then an additional default slave must be implemented to provide a response when any of the nonexistent address locations are accessed
Read data and response multiplexor
Slave Response Signaling
A master cannot cancel a transfer after it has commenced
three slave transfer responses
Transfer done
A successful completed transfer is signaled when HREADY is HIGH and HRESP is OKAY
Transfer pending
It is recommended that slaves do not insert more than 16 wait states, to prevent any single access locking the bus for a large number of clock cycles
ERROR response
Although an OKAY response can be given in a single cycle, the ERROR response requires two cycles
If the slave requires more than two cycles to provide the ERROR response then additional wait states can be inserted at the start of the transfer. During this time HREADY is LOW and the response must be set to OKAY
T3-T4:The master changes the transfer type to IDLE. This cancels the intended transaction to address B, that was registered by a slave at time T2
If a slave provides an ERROR response then the master can cancel the remaining transfers in the burst. However, this is not a strict requirement and it is acceptable for the master to continue the remaining transfers in the burst
Data Buses
Data buses
HWDATA:For transfers that are narrower than the width of the bus, for example a 16-bit transfer on a 32-bit bus, the master only has to drive the appropriate byte lanes.
HRDATA:For transfers that are narrower than the width of the bus, the slave is only required to provide valid data on the active byte lanes.
Endianness
Little endian
Data bus width
Implementing a narrow slave on a wide bus
A slave can only accept transfers that are as wide as its natural interface. If a master attempts a transfer that is wider than the slave can support then the slave can use the ERROR transfer response
Implementing a wide slave on a narrow bus
Implementing a master on a wide bus
The master must never attempt a transfer where the width, as indicated by HSIZE, is wider than the data bus that it connects to
Clock and Reset
During reset all masters must ensure the address and control signals are at valid levels and that HTRANS[1:0]indicates IDLE.
During reset all slaves must ensure that HREADYOUT is HIGH
Exclusive Transfers